Texas Instruments Mixed Signal DV Engineer in Shanghai, China

Job ID 24111BR

Job Posting Title Mixed Signal DV Engineer

Job Description Mixed Signal Design Verification Engineer capable of the following responsibilities:Execute the pre-silicon verification of mixed-signal products

• Create verification plans using datasheets, inputs from engineers/customers, and working closely with systems engineers

. • Implement mixed-signal test-benches in Cadence Virtuoso and/or Verilog-AMS to apply stimulus and checks

. • Implement automatic checks and measurements to verify DUT behavior and populate a Spec Compliance Matrix (SCM)

. • Provide periodic updates on DV status to project participants, management, and customers.

• Work with design and systems teams to close bugs as they arise.

• Drive new and improved methodologies where needed, work with the EDA team to upgrade tools and flows.

• Review the digital and analog design to provide guidance on Design for Verification architecture and features.

Job Opening Type Experienced Professional

Minimum Education Level Bachelor's Level Degree

Related Field(s) of Study

Computer Engineering

Electrical & Computer Engineer

Electrical Engineering

Minimum Years of Experience 2

Regular / Temporary Regular

Full-time / Part-time Full-Time

Country China

Job Location(s) China-Shanghai

Virtual / Telecommute No

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